1. Field of the Invention
The present invention relates to a packaging board and, more particularly, to a packaging board having pad electrodes.
2. Description of the Related Art
Portable electronic devices, such as mobile phones, PDAs, DVCs, and DSCs, are today gaining an increasing variety of functions. And to be accepted by the market, they have to be smaller in size and lighter in weight, and for that reason, there is a growing demand for highly-integrated system LSIs. On the other hand, these electronic devices are expected to be easier or handier to use, and therefore the LSIs used in those devices are required to be more functionally sophisticated and better performing. Thus the higher integration of LSI chips is causing increases in I/O count, which in turn generate demand for smaller packages. To satisfy both these requirements, it is strongly expected that semiconductor packages just right for the high board density packaging of semiconductor parts be developed. In response to such expectations, a variety of packaging technology called CSP (Chip Size Package) are being developed.
BGA (Ball Grid Array) is known as an example of such packaging. In a BGA package, a semiconductor chip is mounted on a substrate for packaging, and after it is resin-molded, solder balls are formed as external terminals in an area array on the opposite face.
FIG. 13 is a schematic cross-sectional view of a conventional BGA-type semiconductor module. This semiconductor device has a semiconductor device 106 mounted on one face of a circuit board 110 and solder balls 112, as external connection terminals, bonded to the other face thereof. Provided on one face of the circuit board 110 is a wiring pattern 103 (pad electrode portion 103a) to be electrically connected to the semiconductor device 106, and provided on the other face thereof is a land portion 103 that bonds the external connection terminal. The wiring pattern 103 and the land portion 103b are electrically coupled through a conductive part provided in the inner wall of a through hole 111 penetrating an insulating substrate 101. A solder resist 105 protects the surface of the circuit board 110. The circuit board 110 is sealed on one face with a molded resin layer 108 after the semiconductor device 106 is mounted thereon.
FIG. 14 is an enlarged sectional view of a pad electrode portion (sectional area indicated by X in FIG. 13) of a semiconductor device as shown in FIG. 13. The pad electrode portion 103a, which is connected by a wire 107, such as gold wire, to a semiconductor device 106, includes a wiring part made of copper and a gold plating layer 104 covering the surface thereof. The solder resist 105 is provided in such a manner as to cover the copper wiring part of the pad electrode portion 103a and also part of the gold plating layer 104. Openings in the solder resist 105 are sealed together with the semiconductor element 106 by the molded resin layer 108 after the semiconductor device 106 is mounted and wire connection and the like are provided.
This construction and arrangement, however, has a problem. The solder resist 105 and the molded resin layer 108, which can prevent external moisture from permeating themselves, cannot prevent moisture from infiltrating along their boundaries. Particularly since the gold plating layer 104 is flat and smooth, the structure can allow moisture to reach the wiring pattern 103 through its interface with the solder resist 105. For this reason, more moisture tends to be found in the part of the wiring pattern 103 near the gold plating layer 104. If the moisture having thus infiltrated further spreads over the surface of the wiring pattern 103, copper ions, which have leaked out from the part of the wiring pattern 103 where a plus voltage is applied during the operation of the semiconductor module, travel along the interface between the insulating substrate 101 and the solder resist 105 and separate out to the part of the wiring pattern 103 where a minus voltage is applied. This so-called ion migration can cause a problem of shorting (dielectric breakdown). This problem presents a great obstacle to improving the reliability of conventional semiconductor modules.